Integrated Circuit ORB (ICO) - Software Defined Radio FPGA

ICO is designed for FPGAs and supports a drop-in Software Defined Radio (SDR) Software Communications Architecture (SCA) compatible interface between distributed software objects running on processors and waveform objects residing in silicon. The connection between Software client and Hardware servant will now be seamless, fast and use fewer system resources.

Using ICO, SCA compliance is maintained and transport overhead is reduced

Overview

Using ICO, one eliminates the need to develop custom proxies on General Purpose Processors (GPPs) and Digital Signal Processors (DSPs) that simply serve to establish communication to waveform objects residing within FPGAs (Field Programmable Gate Arrays). These proxies (sometimes referred to as Hardware Abstraction Layers – HALs) are used when designing to Software Defined Radio (SDR) architectures such as the SCA and are meant to increase portability and re-use, but in practice, they tend to increase latency, reduce throughput, and lower re-use.

ICO further eliminates the need to embed general purpose processing cores into FPGAs in order to offer software ORB capability. Although a viable approach, this approach tends to require significant gate count and memory utilization and generally these processing cores cannot be clocked fast enough to deal with the ever-increasing performance requirements of SDR applications.

The embedded ORB has been written in portable VHDL that can be synthesized onto any FPGA or ASIC platform.

The ICO design environment consists of:
• The ICO engine,
• IDL to VHDL code generator,
• Spectra Modeling Tool,
• The SCA waveform component.

The ICO engine is responsible for implementing the transfer syntax used in CORBA messages. The engine unmarshals the incoming GIOP octet stream and extracts header and data fields while discarding padding. Endian conversion is performed on all incoming data based on information in the GIOP message header. In the incoming direction, the engine performs operation name demultiplexing to determine which object the data in the GIOP message is being transferred to. Message data is then extracted for transfer to the appropriate logic.

If a message indicates that a response is expected, the ICO engine generates a reply message. The engine will perform a read operation to an object, if necessary, to obtain data for the reply. It then populates the header field and aligns the data. When a reply message has been built, the ICO engine transfers the data to the outside world via a FIFO-like interface.

The IDL to VHDL code generator is part of PrismTech’s IDL compiler family. This software tool is responsible for generating configuration parameters needed by the ICO engine to do operation name demultiplexing and data routing to the appropriate objects. The code generator also adds parameters to VHDL package files that configure the physical aspects of the ICO interface and internal storage elements. Parts of the VHDL code for the core are also generated at compile time by the code generator.

In an SCA-complaint environment, ICO communicates with the hardware developer’s native waveform logic via an SCA waveform component. The VHDL for this component is generated by PrismTech’s Spectra Modeling Tool. The PrismTech tools then stitch together the ICO and the SCA waveform component to present the developer with a single core.

The hardware developer treats the ICO as any other IP interface core. The core can be instantiated in the HDL capture of the FPGA design between the native waveform logic and the system bus. The system side of the core appears as a typical FIFO interface. The native side of the core has a simple and open interface to communicate with the waveform logic.

Software developers treat ICO components as they would any other CORBA object. This design approach makes communication between the S/W and H/W objects seamless. Using ICO, radio developers can now host radio elements in an FPGA and still have them be addressable and callable from an SCA-compliant software core framework as though it was an SCA object and not an FPGA.

In the future, it may be possible to do away with the latency introduced by the inefficient transport protocols and send GIOP messages with a minimum of encapsulation via transport mechanisms contained within the FPGAs.

Conclusion

PrismTech has created a powerful solution for implementing real-time CORBA in an SCA environment. The ICO is flexible, highly configurable and uses a minimum of FPGA resources. It frees the hardware developer from learning and implementing the complexities of CORBA protocols and allows concentration on custom waveform design elements. The software engineer is presented with a seamless environment in which to communicate between client and server applications. System developers have a solution that is portable across platforms sharing the same interconnect fabric. The PrismTech ICO represents a significant leap forward in SCA based tools and products.